The average salary for a Mid-Career ASIC Design Engineer in Bangalore, Karnataka is Rs 1,614,683 per year. A skill in Verilog Vhdl is associated with high pay for this job.

Rs 402,683 - Rs 2,383,903
Rs 400K
Rs 2M
Rs 2M
MEDIAN: Rs 1,614,683

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Local Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
Rs 0Rs 1MRs 2MRs 3M
Rs 402,683 - Rs 2,383,903  
Rs 150,000  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
Rs 402,683 - Rs 3,079,209  
Country: India | Currency: INR | Updated: 24 Mar 2017 | Individuals Reporting: 10

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Key Stats for ASIC Design Engineer

5-9 years
10-19 years
Years in Fields/Career:
United States (change)

Skills That Affect ASIC Design Engineer Salaries

Verilog Vhdl

Engineering Design, Semiconductor


National Average
Rs 1,692,000

Common Health Benefits

medical benefits
Medical: 100%
dental benefits
Dental: 33%
vision benefits
Vision: 50%
no benefits