The average pay for an Entry-Level Design Verification Engineer is Rs 612,067 per year. Skills that are associated with high pay for this job are C++ Programming Language and Perl.

Rs 218,380 - Rs 1,520,451
Rs 220K
Rs 620K
Rs 2M
MEDIAN: Rs 619,797
10%
50%
90%
Rs 0Rs 1M
Salary Rs 218,380 - Rs 1,520,451
Bonus Rs -21.52 - Rs 119,195
Profit Sharing Rs 0.00 - Rs 685,100
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 233,015 - Rs 1,653,562
  • Country: India
  • Currency: INR
  • Updated: 24 Jul 2017
  • Individuals Reporting: 139

Find Out Exactly What You Should Be Paid

United States (change)

Design Verification Engineer Job Listings

Pay Difference by Location

National Average: Rs 628,622

Larger city markers indicate a job is popular in that location.

Key Stats for Design Verification Engineer

Gender

Female
5 %
Male
95 %
Less than 1 year
10%
1-4 years
74%
5-9 years
16%
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Location:
Years in Fields/Career:
United States (change)

Skills That Affect Design Verification Engineer Salaries

C++ Programming Language
▲32%

▲25%

National Average
Rs 629,000

System Verilog
▼1%

Verilog Vhdl
▼5%

▼6%

uvm
▼11%

SystemVerilog
▼13%

C++
▼30%

Gender

Female
5 %
Male
95 %

Common Health Benefits

medical benefits
Medical: 64%
dental benefits
Dental: 6%
vision benefits
Vision: 6%
no benefits
None: 36%
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