Entry-Level Design Verification Engineer Salary (India)
The average pay for an Entry-Level Design Verification Engineer is Rs 605,289 per year. Skills that are associated with high pay for this job are Verilog Vhdl, C++ Programming Language, and Perl.
|Range||Rs 0Rs 1M|
|Salary||Rs 186,259 - Rs 1,385,022|
|Bonus||Rs 4,818 - Rs 104,411|
|Profit Sharing||Rs 0.00 - Rs 203,473|
|Total Pay (|
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).)
|Rs 193,451 - Rs 1,438,462|
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