The average pay for an Entry-Level Design Verification Engineer is Rs 612,067 per year. Skills that are associated with high pay for this job are C++ Programming Language and Perl.

Rs 185,921 - Rs 1,381,035
Rs 190K
Rs 610K
Rs 1M
MEDIAN: Rs 612,067
10%
50%
90%

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National Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
Rs 0Rs 500KRs 1MRs 1M
Salary
Rs 185,921 - Rs 1,381,035  
   
Bonus
Rs 5,034 - Rs 117,446  
Profit Sharing
Rs 0.00 - Rs 204,257  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 192,159 - Rs 1,422,359  
Country: India | Currency: INR | Updated: 24 Mar 2017 | Individuals Reporting: 137

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United States (change)

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Pay Difference by Location

National Average: Rs 634,850

Larger city markers indicate a job is popular in that location.

Key Stats for Design Verification Engineer

Gender

Female
7 %
Male
93 %

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 2 votes.
Less than 1 year
9%
1-4 years
76%
5-9 years
15%
Location:
Years in Fields/Career:
United States (change)

Skills That Affect Design Verification Engineer Salaries

C++ Programming Language
▲31%

▲24%

National Average
Rs 635,000

System Verilog
▼2%

Verilog Vhdl
▼5%

▼7%

uvm
▼12%

SystemVerilog
▼13%

C++
▼31%

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 2 votes.

Gender

Female
7 %
Male
93 %

Common Health Benefits

medical benefits
Medical: 64%
dental benefits
Dental: 4%
vision benefits
Vision: 6%
dental benefits
None: 36%
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