The average pay for an Entry-Level Design Verification Engineer is Rs 612,067 per year. A skill in Verilog Vhdl is associated with high pay for this job.

Rs 186,058 - Rs 1,385,022
(Median)
Rs 190K
Rs 610K
Rs 1M
MEDIAN: Rs 612,066
10%
50%
90%

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National Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
Rs 0Rs 500KRs 1MRs 1.5M
Salary
Rs 186,058 - Rs 1,385,022  
   
Bonus
Rs 5,182 - Rs 103,042  
Profit Sharing
Rs 0.00 - Rs 204,257  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 193,946 - Rs 1,437,885  
Country: India | Currency: INR | Updated: 27 Oct 2016 | Individuals Reporting: 139
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Pay Difference by Location

National Average: Rs 636,116

Larger city markers indicate a job is popular in that location.
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Skills That Affect Design Verification Engineer Salaries

Verilog Vhdl
up arrow 41%

Perl
up arrow 4%

National Average
Rs 636,000

System Verilog
up arrow 4%

up arrow 5%

C++ Programming Language
up arrow 8%

uvm
up arrow 16%

C++
up arrow 31%

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 3 votes.

Gender

Female
9 %
Male
91 %

Common Health Benefits

medical benefits
Medical: 68%
dental benefits
Dental: 5%
medical benefits
Vision: 9%
dental benefits
None: 30%
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