The average pay for an Entry-Level Design Verification Engineer is Rs 612,067 per year. Skills that are associated with high pay for this job are C++ Programming Language and Perl.

Rs 187,134 - Rs 1,456,109
Rs 190K
Rs 600K
Rs 2M
MEDIAN: Rs 604,993
10%
50%
90%

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National Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
Rs 0Rs 600KRs 1MRs 1M
Salary
Rs 187,134 - Rs 1,456,109  
   
Bonus
Rs 5,152 - Rs 115,624  
Profit Sharing
Rs 0.00 - Rs 202,028  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 193,608 - Rs 1,508,419  
Country: India | Currency: INR | Updated: 4 May 2017 | Individuals Reporting: 151

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United States (change)

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Pay Difference by Location

National Average: Rs 615,933

Larger city markers indicate a job is popular in that location.

Key Stats for Design Verification Engineer

Gender

Female
7 %
Male
93 %

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 2 votes.
Less than 1 year
10%
1-4 years
74%
5-9 years
16%
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Location:
Years in Fields/Career:
United States (change)

Skills That Affect Design Verification Engineer Salaries

C++ Programming Language
▲35%

▲28%

System Verilog
▲1%

National Average
Rs 616,000

Verilog Vhdl
▼3%

▼4%

uvm
▼9%

SystemVerilog
▼11%

C++
▼29%

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 2 votes.

Gender

Female
7 %
Male
93 %

Common Health Benefits

medical benefits
Medical: 65%
dental benefits
Dental: 4%
vision benefits
Vision: 6%
no benefits
None: 35%
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