Design Verification Engineer with verilog Skills in Bangalore Salary (India)

A Design Verification Engineer with verilog skills in Bangalore, Karnataka earns an average salary of Rs 905,384 per year. Most people with this job move on to other positions after 20 years in this career. Experience strongly influences pay for this job.

Rs 300,667 - Rs 2,394,663
Rs 300K
Rs 1M
Rs 2M
MEDIAN: Rs 1,029,335
10%
50%
90%
Rs 0Rs 2M
Salary Rs 300,667 - Rs 2,394,663
Bonus Rs 0.00 - Rs 300,000
Profit Sharing Rs -21.77 - Rs 295,898
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 300,667 - Rs 2,428,817
  • Country: India
  • Currency: INR
  • Updated: 24 Jul 2017
  • Individuals Reporting: 80

Find Out Exactly What You Should Be Paid

United States (change)

Design Verification Engineer Job Listings

Key Stats for Design Verification Engineer

Gender

Female
3 %
Male
97 %
Less than 1 year
8%
1-4 years
53%
5-9 years
23%
10-19 years
18%
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Location:
Years in Fields/Career:
United States (change)

Experience Affects Design Verification Engineer Salaries

Experienced
▲112%

Mid-Career
▲26%

National Average
Rs 1,115,000

Entry-Level
▼27%

Gender

Female
3 %
Male
97 %

Years of Experience

Less than 1 year
8%
1-4 years
53%
5-9 years
23%
10-19 years
18%

Common Health Benefits

medical benefits
Medical: 70%
dental benefits
Dental: 9%
vision benefits
Vision: 4%
no benefits
None: 28%
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