Design Verification Engineer with verilog Skills in Bangalore Salary (India)

A Design Verification Engineer with verilog skills in Bangalore, Karnataka earns an average salary of Rs 924,234 per year. Most people with this job move on to other positions after 20 years in this career. Experience strongly influences pay for this job.

Rs 179,600 - Rs 2,051,985
Rs 180K
Rs 920K
Rs 2M
MEDIAN: Rs 924,234
10%
50%
90%

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Local Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
Rs 0Rs 800KRs 1MRs 2M
Salary
Rs 179,600 - Rs 2,051,985  
   
Bonus
Rs 0.00 - Rs 450,000  
Profit Sharing
Rs -21.76 - Rs 293,614  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 192,341 - Rs 2,330,151  
Country: India | Currency: INR | Updated: 18 Jan 2017 | Individuals Reporting: 78

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Key Stats for Design Verification Engineer

Gender

Female
6 %
Male
94 %
Less than 1 year
6%
1-4 years
60%
5-9 years
18%
10-19 years
15%
Location:
Years in Fields/Career:
United States (change)

Experience Affects Design Verification Engineer Salaries

Experienced
▲142%

Mid-Career
▲41%

National Average
Rs 974,000

Entry-Level
▼15%

Gender

Female
6 %
Male
94 %

Years of Experience

Less than 1 year
6%
1-4 years
60%
5-9 years
18%
10-19 years
15%

Common Health Benefits

medical benefits
Medical: 77%
dental benefits
Dental: 9%
vision benefits
Vision: 4%
dental benefits
None: 21%
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