Design Verification Engineer in Hyderabad, Andhra Pradesh Salary

A Design Verification Engineer in Hyderabad, Andhra Pradesh earns an average salary of Rs 704,000 per year. Most people move on to other jobs if they have more than 10 years' experience in this career.

Rs 295,898 - Rs 1,562,605
(Median)
Rs 300K
Rs 700K
Rs 2M
MEDIAN: Rs 704,000
10%
50%
90%

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Local Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
Rs 0Rs 600KRs 1.2MRs 1.8M
Salary
Rs 295,898 - Rs 1,562,605  
   
Bonus
Rs 0.00 - Rs 204,257  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 355,077 - Rs 1,702,908  
Country: India | Currency: INR | Updated: 19 Sep 2015 | Individuals Reporting: 27
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Experience Affects Design Verification Engineer Salaries

Mid-Career
up arrow 54%

National Average
Rs 759,000

Entry-Level
up arrow 14%

Skills That Affect Design Verification Engineer Salaries

Verilog Vhdl
up arrow 4%

National Average
Rs 759,000

verilog
up arrow 12%

Perl
up arrow 16%

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 4 votes.

Gender

Female
21 %
Male
79 %

Years of Experience

Less than 1 year
4%
1-4 years
63%
5-9 years
33%

Common Health Benefits

medical benefits
Medical: 75%
dental benefits
Dental: 20%
medical benefits
Vision: 20%
dental benefits
None: 25%
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