Design Verification Engineer in Hyderabad, Andhra Pradesh Salary (India)

A Design Verification Engineer in Hyderabad, Andhra Pradesh earns an average salary of Rs 960,000 per year. People in this job generally don't have more than 10 years' experience. Skills that are associated with high pay for this job are Perl and verilog.

Rs 346,873 - Rs 2,132,542
Rs 350K
Rs 720K
Rs 2M
MEDIAN: Rs 716,860
10%
50%
90%

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Local Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
Rs 0Rs 1MRs 2MRs 3M
Salary
Rs 346,873 - Rs 2,132,542  
   
Bonus
Rs 155,000  
Profit Sharing
Rs 226,006  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 349,049 - Rs 3,026,179  
Country: India | Currency: INR | Updated: 4 May 2017 | Individuals Reporting: 15

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Key Stats for Design Verification Engineer

Gender

Female
14 %
Male
86 %
Less than 1 year
7%
1-4 years
40%
5-9 years
27%
10-19 years
27%
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Location:
Years in Fields/Career:
United States (change)

Experience Affects Design Verification Engineer Salaries

Mid-Career
▲60%

National Average
Rs 729,000

▼11%

Skills That Affect Design Verification Engineer Salaries

Perl
▲187%

verilog
▲78%

Verilog Vhdl
▲8%

National Average
Rs 729,000

Gender

Female
14 %
Male
86 %

Years of Experience

Less than 1 year
7%
1-4 years
40%
5-9 years
27%
10-19 years
27%

Common Health Benefits

medical benefits
Medical: 78%
dental benefits
Dental:
vision benefits
Vision:
no benefits
None: 22%
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