Design Verification Engineer in Hyderabad, Andhra Pradesh Salary (India)

A Design Verification Engineer in Hyderabad, Andhra Pradesh earns an average salary of Rs 960,000 per year. People in this job generally don't have more than 10 years' experience. Skills that are associated with high pay for this job are Perl and verilog.

Rs 370,951 - Rs 2,140,510
Rs 370K
Rs 960K
Rs 2M
MEDIAN: Rs 960,000
10%
50%
90%

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Local Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
Rs 0Rs 1MRs 2MRs 3M
Salary
Rs 370,951 - Rs 2,140,510  
   
Bonus
Rs 150,000  
Profit Sharing
Rs 228,065  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 370,951 - Rs 3,037,486  
Country: India | Currency: INR | Updated: 24 Mar 2017 | Individuals Reporting: 13
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Key Stats for Design Verification Engineer

Gender

Female
14 %
Male
86 %
1-4 years
38%
5-9 years
31%
10-19 years
31%
Location:
Years in Fields/Career:
United States (change)

Experience Affects Design Verification Engineer Salaries

Mid-Career
▲18%

National Average
Rs 990,000

▼34%

Skills That Affect Design Verification Engineer Salaries

Perl
▲111%

verilog
▲31%

National Average
Rs 990,000

Verilog Vhdl
▼21%

Gender

Female
14 %
Male
86 %

Years of Experience

1-4 years
38%
5-9 years
31%
10-19 years
31%

Common Health Benefits

medical benefits
Medical: 70%
dental benefits
Dental:
vision benefits
Vision:
dental benefits
None: 30%
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