Entry-Level Design Verification Engineer with verilog Skills Salary (India)

The average pay for an Entry-Level Design Verification Engineer with verilog skills is Rs 583,790 per year.

Rs 200,668 - Rs 1,560,709
Rs 200K
Rs 590K
Rs 2M
MEDIAN: Rs 587,388
10%
50%
90%
Rs 0Rs 1M
Salary Rs 200,668 - Rs 1,560,709
Bonus Rs 9,910 - Rs 123,650
Profit Sharing Rs 0.00 - Rs 295,898
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 200,668 - Rs 1,674,266
  • Country: India
  • Currency: INR
  • Updated: 10 Jul 2017
  • Individuals Reporting: 75

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United States (change)

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Design Verification Engineer Job Listings

Key Stats for Design Verification Engineer

Gender

Female
7 %
Male
93 %
Less than 1 year
12%
1-4 years
77%
5-9 years
11%
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Location:
Years in Fields/Career:
United States (change)

Gender

Female
7 %
Male
93 %

Common Health Benefits

medical benefits
Medical: 58%
dental benefits
Dental: 6%
vision benefits
Vision: 6%
no benefits
None: 42%
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