Entry-Level Design Verification Engineer with verilog Skills Salary

The average pay for an Entry-Level Design Verification Engineer with verilog skills is Rs 548,791 per year.

Rs 203,155 - Rs 1,009,745
(Median)
Rs 200K
Rs 550K
Rs 1M
MEDIAN: Rs 548,790
10%
50%
90%

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National Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
Rs 0Rs 500KRs 1MRs 1.5M
Salary
Rs 203,155 - Rs 1,009,745  
   
Bonus
Rs -21.50 - Rs 117,446  
Profit Sharing
Rs 9.34 - Rs 97,871  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 211,219 - Rs 1,075,742  
Country: India | Currency: INR | Updated: 19 Sep 2015 | Individuals Reporting: 121
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Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 18 votes.

Gender

Female
9 %
Male
91 %

Common Health Benefits

medical benefits
Medical: 75%
dental benefits
Dental: 6%
medical benefits
Vision: 6%
dental benefits
None: 25%
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