The average salary for a Mid-Career Design Verification Engineer is Rs 1,388,736 per year. A skill in uvm is associated with high pay for this job.

Rs 707,913 - Rs 2,024,427
(Median)
Rs 710K
Rs 1M
Rs 2M
MEDIAN: Rs 1,388,736
10%
50%
90%

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National Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
Rs 0Rs 800KRs 1.6MRs 2.4M
Salary
Rs 707,913 - Rs 2,024,427  
   
Bonus
Rs 0.00 - Rs 247,301  
Profit Sharing
Rs 10,000  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 693,710 - Rs 2,266,924  
Country: India | Currency: INR | Updated: 27 Oct 2016 | Individuals Reporting: 44
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Pay Difference by Location

National Average: Rs 1,398,323

Larger city markers indicate a job is popular in that location.
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Skills That Affect Design Verification Engineer Salaries

uvm
up arrow 17%

National Average
Rs 1,398,000

Verilog Vhdl
up arrow 7%

verilog
up arrow 12%

Perl
up arrow 13%

Gender

Female
13 %
Male
88 %

Common Health Benefits

medical benefits
Medical: 85%
dental benefits
Dental: 11%
medical benefits
Vision: 11%
dental benefits
None: 15%
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