The average salary for a Mid-Career Design Verification Engineer is Rs 1,341,178 per year. The skills that increase pay for this job the most are uvm and SystemVerilog.

Rs 695,305 - Rs 2,042,670
Rs 700K
Rs 1M
Rs 2M
MEDIAN: Rs 1,341,178
10%
50%
90%

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National Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
Rs 0Rs 800KRs 1MRs 2M
Salary
Rs 695,305 - Rs 2,042,670  
   
Bonus
Rs 0.00 - Rs 240,000  
Profit Sharing
Rs 50,000  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 686,951 - Rs 2,367,182  
Country: India | Currency: INR | Updated: 24 Mar 2017 | Individuals Reporting: 50
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Pay Difference by Location

National Average: Rs 1,354,909

Larger city markers indicate a job is popular in that location.

Key Stats for Design Verification Engineer

Gender

Female
11 %
Male
89 %
5-9 years
88%
10-19 years
12%
Location:
Years in Fields/Career:
United States (change)

Skills That Affect Design Verification Engineer Salaries

uvm
▲15%

SystemVerilog
▲11%

National Average
Rs 1,355,000

Verilog Vhdl
▼4%

System Verilog
▼8%

verilog
▼9%

Perl
▼11%

Gender

Female
11 %
Male
89 %

Common Health Benefits

medical benefits
Medical: 82%
dental benefits
Dental: 12%
vision benefits
Vision: 9%
dental benefits
None: 15%
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