Design Verification Engineer with verilog Skills Salary

A Design Verification Engineer with verilog skills earns an average salary of Rs 611,901 per year. Most people move on to other jobs if they have more than 10 years' experience in this field.

Rs 207,392 - Rs 1,489,700
(Median)
Rs 210K
Rs 610K
Rs 2M
MEDIAN: Rs 611,900
10%
50%
90%

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National Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
Rs 0Rs 600KRs 1.2MRs 1.8M
Salary
Rs 207,392 - Rs 1,489,700  
   
Bonus
Rs 986 - Rs 200,534  
Profit Sharing
Rs 0.00 - Rs 87,500  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 221,924 - Rs 1,524,170  
Country: India | Currency: INR | Updated: 19 Sep 2015 | Individuals Reporting: 142
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Design Verification Engineer Job Listings

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Experience Affects Design Verification Engineer Salaries

Mid-Career
up arrow 64%

National Average
Rs 642,000


Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 22 votes.

Gender

Female
9 %
Male
91 %

Years of Experience

Less than 1 year
8%
1-4 years
68%
5-9 years
20%
10-19 years
4%

Common Health Benefits

medical benefits
Medical: 77%
dental benefits
Dental: 7%
medical benefits
Vision: 6%
dental benefits
None: 23%
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