Design Verification Engineer with verilog Skills Salary (India)

The average salary for a Design Verification Engineer with verilog skills is Rs 876,790 per year. Experience strongly influences pay for this job. Most people move on to other jobs if they have more than 20 years' experience in this field.

Rs 281,875 - Rs 2,166,389
Rs 280K
Rs 960K
Rs 2M
MEDIAN: Rs 956,904
10%
50%
90%
Rs 0Rs 2M
Salary Rs 281,875 - Rs 2,166,389
Bonus Rs 9,696 - Rs 252,973
Profit Sharing Rs 0.00 - Rs 237,641
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 281,875 - Rs 2,477,460
  • Country: India
  • Currency: INR
  • Updated: 10 Jul 2017
  • Individuals Reporting: 112

Find Out Exactly What You Should Be Paid

United States (change)

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Design Verification Engineer Job Listings

Pay Difference by Location

National Average: Rs 1,010,181

Larger city markers indicate a job is popular in that location.

Key Stats for Design Verification Engineer

Gender

Female
4 %
Male
96 %
Less than 1 year
8%
1-4 years
52%
5-9 years
22%
10-19 years
18%
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Location:
Years in Fields/Career:
United States (change)

Experience Affects Design Verification Engineer Salaries

Experienced
▲142%

Mid-Career
▲22%

National Average
Rs 1,010,000

▼41%

Gender

Female
4 %
Male
96 %

Years of Experience

Less than 1 year
8%
1-4 years
52%
5-9 years
22%
10-19 years
18%

Common Health Benefits

medical benefits
Medical: 68%
dental benefits
Dental: 11%
vision benefits
Vision: 8%
no benefits
None: 31%
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