Entry-Level Design Verification Engineer in Bangalore Salary (India)

The average pay for an Entry-Level Design Verification Engineer in Bangalore, Karnataka is Rs 806,837 per year. The skills that increase pay for this job the most are C++ Programming Language and Verilog Vhdl.

Rs 193,916 - Rs 1,492,335
Rs 190K
Rs 810K
Rs 2M
MEDIAN: Rs 806,837
10%
50%
90%

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Local Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
Rs 0Rs 600KRs 1MRs 1M
Salary
Rs 193,916 - Rs 1,492,335  
   
Bonus
Rs 9,658 - Rs 119,195  
Profit Sharing
Rs 7,757 - Rs 207,293  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 196,405 - Rs 1,551,313  
Country: India | Currency: INR | Updated: 18 Jan 2017 | Individuals Reporting: 95

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Key Stats for Design Verification Engineer

Gender

Female
3 %
Male
97 %
077
Less than 1 year
8%
1-4 years
78%
5-9 years
14%
Location:
Years in Fields/Career:
United States (change)

Skills That Affect Design Verification Engineer Salaries

C++ Programming Language
up arrow 15%

Verilog Vhdl
up arrow 11%

Perl
up arrow 8%

verilog
up arrow 1%

National Average
Rs 824,000

System Verilog
up arrow 25%

uvm
up arrow 36%

C++
up arrow 39%

Gender

Female
3 %
Male
97 %

Common Health Benefits

medical benefits
Medical: 75%
dental benefits
Dental: 2%
vision benefits
Vision: 6%
dental benefits
None: 25%
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