Senior ASIC Design Engineer with Verilog Vhdl Skills Salary

The average pay for a Senior ASIC Design Engineer with Verilog Vhdl skills is Rs 1,323,208 per year. Most people with this job move on to other positions after 20 years in this career. Experience has a moderate effect on salary for this job.

Rs 815,186 - Rs 2,065,268
(Median)
Rs 820K
Rs 1M
Rs 2M
MEDIAN: Rs 1,323,208
10%
50%
90%

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National Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
Rs 0Rs 900KRs 1.8MRs 2.7M
Salary
Rs 815,186 - Rs 2,065,268  
   
Bonus
Rs 0.00 - Rs 398,665  
Profit Sharing
Rs 50,000  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 824,336 - Rs 2,468,074  
Country: India | Currency: INR | Updated: 19 Sep 2015 | Individuals Reporting: 72
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Experience Affects Senior ASIC Design Engineer Salaries

Experienced
up arrow 68%

Mid-Career
up arrow 2%

National Average
Rs 1,358,000

Entry-Level
up arrow 14%

Job Satisfaction

Extremely satisfied
Rated 5 out of 5
based on 18 votes.

Gender

Female
10 %
Male
90 %

Years of Experience

1-4 years
21%
5-9 years
58%
10-19 years
22%

Common Health Benefits

medical benefits
Medical: 88%
dental benefits
Dental: 21%
medical benefits
Vision: 21%
dental benefits
None: 12%
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