Senior ASIC Design Engineer with Verilog Vhdl Skills Salary (India)

The average pay for a Senior ASIC Design Engineer with Verilog Vhdl skills is Rs 1,587,500 per year. Most people with this job move on to other positions after 20 years in this career. Experience strongly influences salary for this job.

Rs 817,029 - Rs 3,023,248
Rs 820K
Rs 2M
Rs 3M
MEDIAN: Rs 1,587,500
10%
50%
90%

Add this chart to your site: 640px    300px

National Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
Rs 0Rs 1MRs 2MRs 3M
Salary
Rs 817,029 - Rs 3,023,248  
   
Bonus
Rs 98,870  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 817,029 - Rs 3,023,248  
Country: India | Currency: INR | Updated: 18 Jan 2017 | Individuals Reporting: 12

Find Out Exactly What You Should Be Paid

United States (change)

Employers: Start Here »

Senior ASIC Design Engineer Job Listings

Search for more jobs:

Key Stats for Senior ASIC Design Engineer

Gender

Female
17 %
Male
83 %
066
1-4 years
25%
5-9 years
67%
10-19 years
8%
Location:
Years in Fields/Career:
United States (change)

Experience Affects Senior ASIC Design Engineer Salaries

Experienced
up arrow 44%

Mid-Career
up arrow 8%

National Average
Rs 1,587,000

Entry-Level
up arrow 27%

Gender

Female
17 %
Male
83 %

Years of Experience

1-4 years
25%
5-9 years
67%
10-19 years
8%

Common Health Benefits

medical benefits
Medical: 100%
dental benefits
Dental: 20%
vision benefits
Vision: 10%
dental benefits
None:
ADVERTISEMENT