Senior ASIC Design Engineer with Verilog Vhdl Skills Salary (India)

The average pay for a Senior ASIC Design Engineer with Verilog Vhdl skills is Rs 1,600,000 per year. Most people with this job move on to other positions after 20 years in this career. Experience strongly influences salary for this job.

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United States (change)

Senior ASIC Design Engineer Job Listings

Pay Difference by Location

National Average: Rs 1,650,000

Larger city markers indicate a job is popular in that location.

Key Stats for Senior ASIC Design Engineer

Gender

Female
25 %
Male
75 %
1-4 years
25%
5-9 years
63%
10-19 years
13%
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Location:
Years in Fields/Career:
United States (change)

Experience Affects Senior ASIC Design Engineer Salaries

Experienced
▲39%

Mid-Career
▲4%

National Average
Rs 1,650,000

Entry-Level
▼29%

Gender

Female
25 %
Male
75 %

Years of Experience

1-4 years
25%
5-9 years
63%
10-19 years
13%

Common Health Benefits

medical benefits
Medical: 100%
dental benefits
Dental: 33%
vision benefits
Vision: 17%
no benefits
None:
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