Senior ASIC Design Engineer with Verilog Vhdl Skills Salary (India)

The average pay for a Senior ASIC Design Engineer with Verilog Vhdl skills is Rs 1,500,708 per year. Most people with this job move on to other positions after 20 years in this career. Experience strongly influences salary for this job.

Rs 789,061 - Rs 2,736,920
(Median)
Rs 790K
Rs 2M
Rs 3M
MEDIAN: Rs 1,500,707
10%
50%
90%

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National Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
Rs 0Rs 1MRs 2MRs 3M
Salary
Rs 789,061 - Rs 2,736,920  
   
Bonus
Rs 100,000  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 789,061 - Rs 2,838,288  
Country: India | Currency: INR | Updated: 27 Oct 2016 | Individuals Reporting: 17
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Experience Affects Senior ASIC Design Engineer Salaries

Experienced
up arrow 52%

Mid-Career
up arrow 27%

National Average
Rs 1,501,000

Entry-Level
up arrow 22%

Gender

Female
11 %
Male
89 %

Years of Experience

1-4 years
29%
5-9 years
65%
10-19 years
6%

Common Health Benefits

medical benefits
Medical: 100%
dental benefits
Dental: 27%
medical benefits
Vision: 20%
dental benefits
None:
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