The average pay for a Senior ASIC Design Engineer with Verilog Vhdl skills is Rs 1,500,708 per year. Most people with this job move on to other positions after 20 years in this career. Experience strongly influences salary for this job.
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
Rs 789,061 - Rs 2,838,288
Country: India | Currency: INR | Updated: 27 Oct 2016 | Individuals Reporting: 17