Senior ASIC Design Engineer with verilog Skills Salary

The average salary for a Senior ASIC Design Engineer with verilog skills is Rs 1,349,521 per year. Most people with this job move on to other positions after 20 years in this career. Experience strongly influences pay for this job.

Rs 785,115 - Rs 2,438,922
(Median)
Rs 790K
Rs 1M
Rs 2M
MEDIAN: Rs 1,349,520
10%
50%
90%

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National Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
Rs 0Rs 900KRs 1.8MRs 2.7M
Salary
Rs 785,115 - Rs 2,438,922  
   
Bonus
Rs 0.00 - Rs 303,744  
Profit Sharing
Rs 99,477  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 800,000 - Rs 2,571,258  
Country: India | Currency: INR | Updated: 19 Sep 2015 | Individuals Reporting: 89
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Experience Affects Senior ASIC Design Engineer Salaries

Experienced
up arrow 67%

National Average
Rs 1,408,000

Mid-Career
up arrow 2%

Entry-Level
up arrow 19%

Job Satisfaction

Extremely satisfied
Rated 5 out of 5
based on 15 votes.

Gender

Female
7 %
Male
93 %

Years of Experience

1-4 years
18%
5-9 years
61%
10-19 years
21%

Common Health Benefits

medical benefits
Medical: 81%
dental benefits
Dental: 12%
medical benefits
Vision: 7%
dental benefits
None: 19%
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