Senior ASIC Design Engineer with verilog Skills Salary (India)

The average salary for a Senior ASIC Design Engineer with verilog skills is Rs 1,272,888 per year. Most people with this job move on to other positions after 20 years in this career. Experience has a moderate effect on pay for this job.

Rs 793,968 - Rs 2,553,215
Rs 790K
Rs 1M
Rs 3M
MEDIAN: Rs 1,272,888
10%
50%
90%

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National Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
Rs 0Rs 900KRs 1MRs 2M
Salary
Rs 793,968 - Rs 2,553,215  
   
Bonus
Rs 50,000  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 805,366 - Rs 2,553,215  
Country: India | Currency: INR | Updated: 24 Mar 2017 | Individuals Reporting: 16

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Pay Difference by Location

National Average: Rs 1,272,888

Larger city markers indicate a job is popular in that location.

Key Stats for Senior ASIC Design Engineer

Gender

Female
11 %
Male
89 %
1-4 years
31%
5-9 years
63%
10-19 years
6%
Location:
Years in Fields/Career:
United States (change)

Experience Affects Senior ASIC Design Engineer Salaries

Experienced
▲85%

Mid-Career
▲57%

National Average
Rs 1,273,000

Entry-Level
▼2%

Gender

Female
11 %
Male
89 %

Years of Experience

1-4 years
31%
5-9 years
63%
10-19 years
6%

Common Health Benefits

medical benefits
Medical: 100%
dental benefits
Dental: 18%
vision benefits
Vision: 18%
dental benefits
None:
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