Senior ASIC Design Engineer with verilog Skills Salary (India)

The average salary for a Senior ASIC Design Engineer with verilog skills is Rs 1,272,888 per year. Most people with this job move on to other positions after 20 years in this career. Experience has a moderate effect on pay for this job.

Rs 789,061 - Rs 2,681,891
Rs 790K
Rs 1M
Rs 3M
MEDIAN: Rs 1,224,888
10%
50%
90%
Rs 0Rs 2M
Salary Rs 789,061 - Rs 2,681,891
Bonus Rs 30,339
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 789,061 - Rs 2,681,891
  • Country: India
  • Currency: INR
  • Updated: 10 Jul 2017
  • Individuals Reporting: 10

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United States (change)

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Senior ASIC Design Engineer Job Listings

Pay Difference by Location

National Average: Rs 1,244,888

Larger city markers indicate a job is popular in that location.

Key Stats for Senior ASIC Design Engineer

1-4 years
30%
5-9 years
70%
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Location:
Years in Fields/Career:
United States (change)

Experience Affects Senior ASIC Design Engineer Salaries

Experienced
▲89%

Mid-Career
▲61%

Entry-Level
▼0%

National Average
Rs 1,245,000

Years of Experience

1-4 years
30%
5-9 years
70%

Common Health Benefits

medical benefits
Medical: 100%
dental benefits
Dental: 29%
vision benefits
Vision: 29%
no benefits
None:
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