Senior ASIC Design Engineer with verilog Skills Salary (India)

The average salary for a Senior ASIC Design Engineer with verilog skills is Rs 1,471,095 per year. Most people with this job move on to other positions after 20 years in this career. Experience strongly influences pay for this job.

Rs 823,330 - Rs 2,516,767
(Median)
Rs 820K
Rs 2M
Rs 3M
MEDIAN: Rs 1,471,095
10%
50%
90%

Add this chart to your site: 640px    300px

National Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
Rs 0Rs 900KRs 1.8MRs 2.7M
Salary
Rs 823,330 - Rs 2,516,767  
   
Bonus
Rs 39,453 - Rs 297,988  
Profit Sharing
Rs 50,868  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 866,050 - Rs 2,642,528  
Country: India | Currency: INR | Updated: 27 Oct 2016 | Individuals Reporting: 22

Find Out Exactly What You Should Be Paid

United States (change)

Comp Managers: Start Here »

Senior ASIC Design Engineer Job Listings

Search for more jobs:

Location:
Years in Fields/Career:
United States (change)

Experience Affects Senior ASIC Design Engineer Salaries

Experienced
up arrow 49%

Mid-Career
up arrow 9%

National Average
Rs 1,585,000

Entry-Level
up arrow 15%

Gender

Female
8 %
Male
92 %

Years of Experience

1-4 years
36%
5-9 years
59%
10-19 years
5%

Common Health Benefits

medical benefits
Medical: 100%
dental benefits
Dental: 17%
medical benefits
Vision: 17%
dental benefits
None:
ADVERTISEMENT