Mid-Career Senior ASIC Design Engineer in Bangalore Salary (India)

The average pay for a Mid-Career Senior ASIC Design Engineer in Bangalore, Karnataka is Rs 1,744,811 per year. A skill in Verilog Vhdl is associated with high pay for this job.

Rs 978,714 - Rs 2,575,745
(Median)
Rs 980K
Rs 2M
Rs 3M
MEDIAN: Rs 1,744,811
10%
50%
90%

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Local Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
Rs 0Rs 1MRs 2MRs 3M
Salary
Rs 978,714 - Rs 2,575,745  
   
Bonus
Rs -21.75 - Rs 290,874  
Profit Sharing
Rs 52,381  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 1,076,585 - Rs 2,705,361  
Country: India | Currency: INR | Updated: 27 Oct 2016 | Individuals Reporting: 28
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Skills That Affect Senior ASIC Design Engineer Salaries

Verilog Vhdl
up arrow 11%

National Average
Rs 1,895,000

verilog
up arrow 3%

Engineering Design, Semiconductor
up arrow 11%

Gender

Female
15 %
Male
85 %

Common Health Benefits

medical benefits
Medical: 100%
dental benefits
Dental: 14%
medical benefits
Vision: 5%
dental benefits
None:
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