Average Salary for Skill: Verilog Vhdl

Skill: Verilog Vhdl Median Salary by Job
Job
National Salary Data 
Rs 0Rs 600KRs 1MRs 1M
Design Verification Engineer
46 salaries
Rs 898,902  
   
Design Engineer
36 salaries
Rs 600,000  
ASIC Design Engineer
12 salaries
Rs 819,512  
Senior ASIC Design Engineer
8 salaries
Rs 1,600,000  
Verification Specialist
3 salaries
Rs 850,000  
Staff Engineer
2 salaries
Rs 1,709,500  
Very-Large-Scale Integration (VLSI) Engineer
2 salaries
Rs 738,000  
Country: India | Currency: INR | Updated: 22 Apr 2017 | Individuals Reporting: 133

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