Average Salary for Skill: Verilog Vhdl

Skill: Verilog Vhdl Median Salary by Job
National Salary Data 
Rs 0Rs 900KRs 1MRs 2M
Design Verification EngineerRs 984,533  
Design EngineerRs 604,024  
ASIC Design EngineerRs 700,000  
Staff EngineerRs 1,850,000  
Senior ASIC Design EngineerRs 2,700,000  
Verification SpecialistRs 850,000  
Field Application EngineerRs 329,000  
Country: India | Currency: INR | Updated: 12 Aug 2017 | Individuals Reporting: 138

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