Average Salary for Skill: Verilog Vhdl

Skill: Verilog Vhdl Median Salary by Job
Job
National Salary Data 
Rs 0Rs 900KRs 1.8MRs 2.7M
Design Verification Engineer
42 salaries
Rs 911,592  
   
Design Engineer
35 salaries
Rs 589,581  
ASIC Design Engineer
14 salaries
Rs 740,000  
Senior ASIC Design Engineer
13 salaries
Rs 1,500,708  
Senior ASIC Engineer
3 salaries
Rs 2,495,502  
Staff Engineer
3 salaries
Rs 1,850,000  
Very-Large-Scale Integration (VLSI) Engineer
2 salaries
Rs 1,058,000  
Country: India | Currency: INR | Updated: 3 Dec 2016 | Individuals Reporting: 136
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