Average Salary for Skill: Verilog Vhdl

Skill: Verilog Vhdl Median Salary by Job
Job
National Salary Data 
Rs 0Rs 700KRs 1MRs 2M
Design Verification EngineerRs 940,746  
   
Design EngineerRs 595,976  
ASIC Design EngineerRs 799,918  
Senior ASIC Design EngineerRs 1,902,000  
Verification SpecialistRs 850,000  
Field Application EngineerRs 329,000  
Senior Electronics Design EngineerRs 2,036,000  
Country: India | Currency: INR | Updated: 16 Jul 2017 | Individuals Reporting: 134

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