ASIC Design Engineer with Verilog Vhdl Skills Salary
The average pay for an ASIC Design Engineer with Verilog Vhdl skills is $98,114 per year. Most people with this job move on to other positions after 20 years in this field. Experience has a moderate effect on salary for this job.
|Salary||$66,731 - $142,950|
|Bonus||$0.00 - $20,134|
|Total Pay (||$68,815 - $149,012|
ASIC Design Engineer Job Listings
Key Stats for ASIC Design Engineer