ASIC Design Engineer with Verilog Vhdl Skills Salary

The average pay for an ASIC Design Engineer with Verilog Vhdl skills is $98,114 per year. Most people with this job move on to other positions after 20 years in this field. Experience has a moderate effect on salary for this job.

$66,731 - $142,950
$67K
$100K
$140K
MEDIAN: $101,604
10%
50%
90%

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$0$149K
Salary $66,731 - $142,950
Bonus $0.00 - $20,134
Profit Sharing $4,000
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
$68,815 - $149,012
  • Country: United States
  • Currency: USD
  • Updated: 11 Jul 2017
  • Individuals Reporting: 26

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United States (change)

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ASIC Design Engineer Job Listings

Key Stats for ASIC Design Engineer

Gender

Female
18 %
Male
82 %
Less than 1 year
14%
1-4 years
32%
5-9 years
29%
10-19 years
21%
20 years or more
4%
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Location:
Years in Fields/Career:
United States (change)

Experience Affects ASIC Design Engineer Salaries

Experienced
▲16%

National Average
$103,000

Mid-Career
▼1%

Entry-Level
▼18%

Gender

Female
18 %
Male
82 %

Years of Experience

Less than 1 year
14%
1-4 years
32%
5-9 years
29%
10-19 years
21%
20 years or more
4%

Common Health Benefits

medical benefits
Medical: 88%
dental benefits
Dental: 76%
vision benefits
Vision: 76%
no benefits
None: 8%
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