ASIC Design Engineer with Verilog Vhdl Skills Salary
The average pay for an ASIC Design Engineer with Verilog Vhdl skills is $98,114 per year. Most people with this job move on to other positions after 20 years in this field. Experience has a moderate effect on salary for this job.
|Salary||$63,887 - $143,908|
|Bonus||$0.00 - $20,067|
|Total Pay (|
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).)
|$66,776 - $149,300|
Key Stats for ASIC Design Engineer