ASIC Design Engineer with Verilog Vhdl Skills Salary

The average pay for an ASIC Design Engineer with Verilog Vhdl skills is $98,114 per year. Most people with this job move on to other positions after 20 years in this field. Experience has a moderate effect on salary for this job.

$63,887 - $143,908
$64K
$98K
$140K
MEDIAN: $98,114
10%
50%
90%

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National Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
$0$50K$100K$150K
Salary
$63,887 - $143,908  
   
Bonus
$0.00 - $20,067  
Profit Sharing
$4,000  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
$66,776 - $149,300  
Country: United States | Currency: USD | Updated: 25 Mar 2017 | Individuals Reporting: 25

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Key Stats for ASIC Design Engineer

Gender

Female
19 %
Male
81 %
Less than 1 year
15%
1-4 years
33%
5-9 years
33%
10-19 years
15%
20 years or more
4%
Location:
Years in Fields/Career:
United States (change)

Experience Affects ASIC Design Engineer Salaries

Experienced
▲16%

National Average
$103,000

Mid-Career
▼1%

Entry-Level
▼17%

Gender

Female
19 %
Male
81 %

Years of Experience

Less than 1 year
15%
1-4 years
33%
5-9 years
33%
10-19 years
15%
20 years or more
4%

Common Health Benefits

medical benefits
Medical: 83%
dental benefits
Dental: 65%
vision benefits
Vision: 65%
no benefits
None: 13%