Design Verification Engineer Salary (United States)

The average pay for a Design Verification Engineer is $93,050 per year. People in this job generally don't have more than 20 years' experience. Experience has a moderate effect on salary for this job.
Design Verification Engineer Total Pay (?
XAll compensation data shown are gross, national 10th to 90th percentile ranges. Pay can vary greatly by location. To view local data, take the PayScale survey.
)
$68,385 - $134,007
(Median)
68K
93K
110K
130K
MEDIAN: $93,049
10%
50%
75%
90%
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Design Verification Engineer Total Pay (?
XAll compensation data shown are gross, national 10th to 90th percentile ranges. Pay can vary greatly by location. To view local data, take the PayScale survey.
)
$26.79 - $77.57
(Median)
27
61
78
MEDIAN: $38.00
10%
75%
90%
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National Salary Data

 (?
XAll compensation data shown are gross, national 10th to 90th percentile ranges. Pay can vary greatly by location. To view local data, take the PayScale survey.
)
$0$50K$100K$150K
Salary
$68,385 - $134,007  
   
Bonus
$0.00 - $15,347  
Profit Sharing
$997 - $9,696  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
$69,671 - $141,926  
PayScale
Country: United States | Currency: USD | Updated: 11 Jun 2014 | Individuals Reporting: 361
National Hourly Rate Data (?
XAll compensation data shown are gross, national 10th to 90th percentile ranges. Pay can vary greatly by location. To view local data, take the PayScale survey.
)
$0$26$52$78
Hourly Rate
$26.79 - $77.57  
   
National Annualized Data (?
XAll compensation data shown are gross, national 10th to 90th percentile ranges. Pay can vary greatly by location. To view local data, take the PayScale survey.
)
$0$60K$120K$180K
Bonus
$0.00 - $15,347  
   
Profit Sharing
$997 - $9,696  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
$69,671 - $141,926  
PayScale
Country: United States | Currency: USD | Updated: 11 Jun 2014 | Individuals Reporting: 361
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Job Description for Design Verification Engineer

A design verification engineer works to debug and verify designs and potential products as needed by their company. They attempt to identify and solve as many problems as possible with a product before its public launch; this includes using products in other ways than intended use to identify safety concerns, design flaws, and problem areas. A design verification engineer must be able to work on a wide range of projects in a variety of areas.
Read More...
Design Verification Engineer Tasks
  • Create scripts to automate and test processes.
  • Write verification plans, test them and improve methodologies and toolsets.
  • Develop verification environments and processes.
  • Explain and communicate verification needs and results.

Design Verification Engineer Job Listings

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Popular Employer Salaries for Design Verification Engineer

Popular Skills for Design Verification Engineer

Pay by Experience Level for Design Verification Engineer

Median of all compensation (including tips, bonus, and overtime) by years of experience.

Pay Difference By Location

Cupertino
up arrow 29%
up arrow 11%
up arrow 1%
San Diego
up arrow 1%
National Average
$97,000
Sunnyvale
up arrow 10%
Dallas
up arrow 25%
Larger circles over a city indicate a job is popular in that location.

Related Job Salaries

Experience Affects Design Verification Engineer Salaries

Late-Career
up arrow 43%
National Average
$97,000

Skills That Affect Design Verification Engineer Salaries

SystemVerilog
up arrow 3%
Perl
up arrow 2%
verilog
up arrow 1%
National Average
$97,000
Verilog Vhdl
up arrow 3%
uvm
up arrow 3%
C++
up arrow 4%
System Verilog
up arrow 5%
C
up arrow 9%
Board Design / Debug
up arrow 10%

Job Satisfaction

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Highly satisfied
Rated 4 out of 5 based on 59 votes.

Gender

Female
11%
female alumni
 
Male
89%
male alumni

Years of Experience

Less than 1 year
6%
1-4 years
39%
5-9 years
22%
10-19 years
28%
20 years or more
6%

Common Health Benefits

medical benefits Medical: 94% dental benefits Dental: 82%
vision benefits Vision: 71% employee benefits None: 5%
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