Design Verification Engineer Salary

Average Design Verification Engineers in the United States make around $96K per year. Overall cash earnings for Design Verification Engineers stretch from $70K on the lower end to $139K near the top, and the heftiest packages can encompass around $15K from bonuses and $10K from profit sharing. Compensation for this group is mainly affected by career duration, but the particular city and the individual firm are influential factors as well. Most people on this career path report moderate levels of job satisfaction. The vast majority (85 percent) of Design Verification Engineers who answered the questionnaire are male. Almost all enjoy medical while a fair number get dental coverage. Vision coverage is also available to a strong majority. Participants in PayScale's salary questionnaire provided the particulars of this report.

$69,422 - $132,481
(Median)
$69K
$96K
$130K
MEDIAN: $95,908
10%
50%
90%

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$27.17 - $66.98
(Median)
$27
$38
$67
MEDIAN: $37.00
10%
50%
90%

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National Salary Data (?
XAll compensation data shown are gross, national 10th to 90th percentile ranges. Pay can vary greatly by location. To view local data, take the PayScale survey.
)
$0$50K$100K$150K
Salary
$69,422 - $132,481  
   
Bonus
$0.00 - $15,367  
Profit Sharing
$997 - $10,033  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
$70,471 - $139,470  
Country: United States | Currency: USD | Updated: 2 Jul 2015 | Individuals Reporting: 389
National Hourly Rate Data (?
XAll compensation data shown are gross, national 10th to 90th percentile ranges. Pay can vary greatly by location. To view local data, take the PayScale survey.
)
$0$25$50$75
Hourly Rate
$27.17 - $66.98  
   
Overtime
$39.25 - $67.25  
National Annualized Data (?
XAll compensation data shown are gross, national 10th to 90th percentile ranges. Pay can vary greatly by location. To view local data, take the PayScale survey.
)
$0$50K$100K$150K
Bonus
$0.00 - $15,367  
   
Profit Sharing
$997 - $10,033  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
$70,471 - $139,470  
Country: United States | Currency: USD | Updated: 2 Jul 2015 | Individuals Reporting: 15
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Job Description for Design Verification Engineer

A design verification engineer works to debug and verify designs and potential products as needed by their company. They attempt to identify and solve as many problems as possible with a product before its public launch; this includes using products in other ways than intended use to identify safety concerns, design flaws, and problem areas. A design verification engineer must be able to work on a wide range of projects in a variety of areas.

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Design Verification Engineer Tasks

  • Create scripts to automate and test processes.
  • Write verification plans, test them and improve methodologies and toolsets.
  • Develop verification environments and processes.
  • Explain and communicate verification needs and results.

Design Verification Engineer Job Listings

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Popular Employer Salaries for Design Verification Engineer


Design Verification Engineers seeking a sizable paycheck can earn the most at Broadcom Corporation, where the median salary comes to $109K, though the large pay difference between employees at the top ($79K) and those starting out ($149K) creates a rather diverse pay scale.

Popular Skills for Design Verification Engineer


Survey results imply that Design Verification Engineers put a diverse skill set to use. Most notably, skills in SystemVerilog, verilog, Board Design / Debug, and Perl are correlated to pay that is above average. Skills that are correlated to lower pay, on the other hand, include System Verilog, C++, and C. For most people, competency in C++ indicates knowledge of Perl.

Pay by Experience Level for Design Verification Engineer

Median of all compensation (including tips, bonus, and overtime) by years of experience.


Experience and income seem to be closely related; in general, the survey respondents who had worked for more years reported higher incomes. In this occupation, salaries for the relatively untested average out to $88K, but folks in the five-to-10 year range enjoy a much heftier median of $103K. Design Verification Engineers with one to two decades of relevant experience report an average salary of approximately $125K. People who have worked for more than 20 years report a median income of $137K, which is barely higher than the median for folks with 10 to 20 years of experience.

Pay Difference by Location


Santa Clara offers some of the highest pay in the country for Design Verification Engineers, 21 percent above the national average. Design Verification Engineers will also find cushy salaries in San Diego (+15 percent), Cupertino (+8 percent), Sunnyvale (+4 percent), and San Jose (+2 percent). Design Verification Engineers in Dallas take home the lowest salaries, earning a whopping 22 percent less than the national average. Workers in Raleigh and Folsom earn salaries that trail the national average for those in this profession (9 percent less and 5 percent less, respectively).

Design Verification Engineer Reviews

What is it like working as a Design Verification Engineer?

Design Verification Engineer in San Jose:
"Nice team however the product is not doing good in market."
Pros: Team mates are very experienced and highly motivating.
Cons: The possibility to learn new things is not vast. We are made to work on same tasks over spread of different projects with minor modifications.

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Experience Affects Design Verification Engineer Salaries

Late-Career
up arrow 39%



National Average
$99,000


Skills That Affect Design Verification Engineer Salaries

SystemVerilog
up arrow 1%

verilog
0%

Board Design / Debug
0%

National Average
$99,000

Perl
up arrow 1%

Verilog Vhdl
up arrow 2%

uvm
up arrow 3%

C
up arrow 5%

C++
up arrow 6%

System Verilog
up arrow 7%

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 55 votes.

Gender

Female
15 %
Male
85 %

Years of Experience

Less than 1 year
8%
1-4 years
41%
5-9 years
21%
10-19 years
25%
20 years or more
6%

Common Health Benefits

medical benefits Medical: 94% dental benefits Dental: 79%
vision benefits Vision: 71% employee benefits None: 5%
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