Experienced Design Verification Engineer Salary

The average pay for an Experienced Design Verification Engineer is $127,619 per year. A skill in uvm is associated with high pay for this job.

$106,427 - $163,823
$110K
$130K
$160K
MEDIAN: $129,469
10%
50%
90%

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$0$176K
Salary $106,427 - $163,823
Bonus $3,673 - $27,148
Profit Sharing $970 - $13,709
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
$114,223 - $176,600
  • Country: United States
  • Currency: USD
  • Updated: 25 Jul 2017
  • Individuals Reporting: 63

Find Out Exactly What You Should Be Paid

United States (change)

Design Verification Engineer Job Listings

Key Stats for Design Verification Engineer

Gender

Female
17 %
Male
83 %

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 6 votes.
10-19 years
92%
20 years or more
8%
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Location:
Years in Fields/Career:
United States (change)

Skills That Affect Design Verification Engineer Salaries

uvm
▲23%

▼0%

National Average
$142,000

Engineering Design, Semiconductor
▼2%

Perl
▼4%

C++ Programming Language
▼5%

C programming Language
▼7%

Verilog Vhdl
▼8%

Board Design / Debug
▼14%

C++
▼15%

C
▼20%

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 6 votes.

Gender

Female
17 %
Male
83 %

Common Health Benefits

medical benefits
Medical: 92%
dental benefits
Dental: 87%
vision benefits
Vision: 87%
no benefits
None: 6%
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