Experienced Design Verification Engineer Salary

The average pay for an Experienced Design Verification Engineer is $127,619 per year. A skill in uvm is associated with high pay for this job.

$102,971 - $161,317
$100K
$130K
$160K
MEDIAN: $127,784
10%
50%
90%

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National Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
$0$60K$120K$180K
Salary
$102,971 - $161,317  
   
Bonus
$2,970 - $27,284  
Profit Sharing
$500 - $13,734  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
$110,732 - $176,485  
Country: United States | Currency: USD | Updated: 4 May 2017 | Individuals Reporting: 62

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Key Stats for Design Verification Engineer

Gender

Female
19 %
Male
81 %

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 6 votes.
10-19 years
95%
20 years or more
5%
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Location:
Years in Fields/Career:
United States (change)

Skills That Affect Design Verification Engineer Salaries

uvm
▲26%

▲3%

Engineering Design, Semiconductor
▼0%

National Average
$138,000

Perl
▼1%

C++ Programming Language
▼2%

C programming Language
▼4%

Verilog Vhdl
▼6%

Board Design / Debug
▼12%

C++
▼13%

C
▼18%

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 6 votes.

Gender

Female
19 %
Male
81 %

Common Health Benefits

medical benefits
Medical: 92%
dental benefits
Dental: 86%
vision benefits
Vision: 86%
no benefits
None: 6%
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