Design Verification Engineer with verilog Skills in San Jose, California Salary

The average pay for a Design Verification Engineer with verilog skills in San Jose, California is $111,412 per year. Most people with this job move on to other positions after 20 years in this field.

$78,955 - $146,039
(Median)
$79K
$110K
$150K
MEDIAN: $111,412
10%
50%
90%

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Local Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
$0$60K$120K$180K
Salary
$78,955 - $146,039  
   
Bonus
$10.07 - $20,273  
Profit Sharing
$9,250  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
$86,989 - $161,363  
Country: United States | Currency: USD | Updated: 28 Oct 2016 | Individuals Reporting: 32
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Design Verification Engineer Job Listings

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Experience Affects Design Verification Engineer Salaries

Experienced
up arrow 16%

Mid-Career
up arrow 8%

National Average
$119,000

Entry-Level
up arrow 16%

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 6 votes.

Gender

Female
26 %
Male
74 %

Years of Experience

Less than 1 year
6%
1-4 years
38%
5-9 years
41%
10-19 years
13%
20 years or more
3%

Common Health Benefits

medical benefits
Medical: 96%
dental benefits
Dental: 77%
medical benefits
Vision: 65%
dental benefits
None: 4%
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