Senior ASIC Design Engineer with Verilog Vhdl Skills Salary

The average salary for a Senior ASIC Design Engineer with Verilog Vhdl skills is $121,306 per year.

$96,354 - $151,889
$96K
$120K
$150K
MEDIAN: $119,650
10%
50%
90%

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$0$160K
Salary $96,354 - $151,889
Bonus $13,400
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
$96,354 - $160,188
  • Country: United States
  • Currency: USD
  • Updated: 25 Jul 2017
  • Individuals Reporting: 15

Find Out Exactly What You Should Be Paid

United States (change)

Senior ASIC Design Engineer Job Listings

Pay Difference by Location

National Average: $121,652

Larger city markers indicate a job is popular in that location.

Key Stats for Senior ASIC Design Engineer

Job Satisfaction

Extremely satisfied
Rated 5 out of 5
based on 2 votes.
1-4 years
7%
5-9 years
13%
10-19 years
67%
20 years or more
13%
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Location:
Years in Fields/Career:
United States (change)

Experience Affects Senior ASIC Design Engineer Salaries

Experienced
▲4%

National Average
$122,000

Late-Career
▼3%

Entry-Level
▼15%

Job Satisfaction

Extremely satisfied
Rated 5 out of 5
based on 2 votes.

Years of Experience

1-4 years
7%
5-9 years
13%
10-19 years
67%
20 years or more
13%

Common Health Benefits

medical benefits
Medical: 100%
dental benefits
Dental: 92%
vision benefits
Vision: 77%
no benefits
None:
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