Senior ASIC Design Engineer with Verilog Vhdl Skills Salary

The average salary for a Senior ASIC Design Engineer with Verilog Vhdl skills is $121,306 per year.

$101,186 - $150,106
$100K
$120K
$150K
MEDIAN: $121,306
10%
50%
90%

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National Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
$0$60K$120K$180K
Salary
$101,186 - $150,106  
   
Bonus
$13,400  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
$101,367 - $158,742  
Country: United States | Currency: USD | Updated: 25 Mar 2017 | Individuals Reporting: 18

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Pay Difference by Location

National Average: $125,506

Larger city markers indicate a job is popular in that location.

Key Stats for Senior ASIC Design Engineer

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 3 votes.
1-4 years
6%
5-9 years
6%
10-19 years
72%
20 years or more
17%
Location:
Years in Fields/Career:
United States (change)

Experience Affects Senior ASIC Design Engineer Salaries

Experienced
▲1%

National Average
$126,000

Late-Career
▼6%

Entry-Level
▼18%

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 3 votes.

Years of Experience

1-4 years
6%
5-9 years
6%
10-19 years
72%
20 years or more
17%

Common Health Benefits

medical benefits
Medical: 100%
dental benefits
Dental: 93%
vision benefits
Vision: 80%
no benefits
None: