Average Salary for Skill: Verilog Vhdl

Verilog Vhdl Median Salary by Job

MinMax

Electrical Engineer
2 profiles
C$101,000
C$0C$101K

Software Engineer
2 profiles
C$87,429
C$0C$87K

Design Verification Engineer
2 profiles
C$62,300
C$0C$62K

Canada (change)

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  • Country: Canada
  • Currency: CAD
  • Updated: 14 Oct 2017
  • Individuals Reporting: 12
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