Design Verification Engineer with verilog Skills in Bangalore Salary (India)

A Design Verification Engineer with verilog skills in Bangalore, Karnataka earns an average salary of Rs 905,384 per year. Most people with this job move on to other positions after 20 years in this career. Experience strongly influences pay for this job.

Rs 302,524 - Rs 2,445,215
Rs 300K
Rs 1M
Rs 2M
MEDIAN: Rs 1,081,683
10%
50%
90%
Rs 0Rs 2M
Salary Rs 302,524 - Rs 2,445,215
Bonus Rs -21.64 - Rs 484,790
Profit Sharing Rs -21.76 - Rs 293,614
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 302,524 - Rs 2,504,164
  • Country: India
  • Currency: INR
  • Updated: 14 Oct 2017
  • Individuals Reporting: 79

Design Verification Engineer Job Listings

Key Stats for Design Verification Engineer

Gender

Female
3 %
Male
97 %
Less than 1 year
8%
1-4 years
48%
5-9 years
28%
10-19 years
16%

Experience Affects Design Verification Engineer Salaries

Experienced
▲103%

Mid-Career
▲21%

National Average
Rs 1,161,000

Entry-Level
▼30%

Gender

Female
3 %
Male
97 %

Years of Experience

Less than 1 year
8%
1-4 years
48%
5-9 years
28%
10-19 years
16%

Common Health Benefits

medical benefits
Medical: 70%
dental benefits
Dental: 9%
vision benefits
Vision: 4%
no benefits
None: 28%