Entry-Level Design Verification Engineer with verilog Skills Salary (India)

The average pay for an Entry-Level Design Verification Engineer with verilog skills is Rs 583,790 per year.

Rs 249,033 - Rs 1,551,978
Rs 250K
Rs 590K
Rs 2M
MEDIAN: Rs 591,899
10%
50%
90%
Rs 0Rs 1M
Salary Rs 249,033 - Rs 1,551,978
Bonus Rs 9,933 - Rs 163,406
Profit Sharing Rs 0.00 - Rs 275,000
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 249,033 - Rs 1,724,883
  • Country: India
  • Currency: INR
  • Updated: 18 Nov 2017
  • Individuals Reporting: 78

Design Verification Engineer Job Listings

Key Stats for Design Verification Engineer

Gender

Female
6 %
Male
94 %
Less than 1 year
12%
1-4 years
74%
5-9 years
14%

Gender

Female
6 %
Male
94 %

Common Health Benefits

medical benefits
Medical: 56%
dental benefits
Dental: 5%
vision benefits
Vision: 5%
no benefits
None: 44%