Entry-Level Design Verification Engineer with verilog Skills Salary (India)

The average pay for an Entry-Level Design Verification Engineer with verilog skills is Rs 583,790 per year.

Rs 241,902 - Rs 1,575,779
Rs 240K
Rs 580K
Rs 2M
MEDIAN: Rs 575,849
10%
50%
90%
Rs 0Rs 1M
Salary Rs 241,902 - Rs 1,575,779
Bonus Rs 10,090 - Rs 155,737
Profit Sharing Rs 0.00 - Rs 293,614
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 241,902 - Rs 1,743,853
  • Country: India
  • Currency: INR
  • Updated: 21 Oct 2017
  • Individuals Reporting: 71

Design Verification Engineer Job Listings

Key Stats for Design Verification Engineer

Gender

Female
7 %
Male
93 %
Less than 1 year
13%
1-4 years
75%
5-9 years
13%

Gender

Female
7 %
Male
93 %

Common Health Benefits

medical benefits
Medical: 60%
dental benefits
Dental: 6%
vision benefits
Vision: 6%
no benefits
None: 40%