Senior ASIC Design Engineer with verilog Skills Salary (India)
The average salary for a Senior ASIC Design Engineer with verilog skills is Rs 1,272,888 per year. Most people with this job move on to other positions after 20 years in this career. Experience has a moderate effect on pay for this job.
|Range||Rs 0Rs 2M|
|Salary||Rs 789,061 - Rs 2,681,891|
|Total Pay (|
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).)
|Rs 789,061 - Rs 2,681,891|