Average Salary for Skill: Verilog Vhdl

Verilog Vhdl Median Salary by Job

MinMax

Design Verification Engineer
49 profiles
Rs 1,035,930
Rs 363KRs 2.6M

Design Engineer
40 profiles
Rs 650,000
Rs 157KRs 1.7M

ASIC Design Engineer
10 profiles
Rs 575,000
Rs 242KRs 1.8M

India (change)

Staff Engineer
4 profiles
Rs 2,437,500
Rs 0Rs 2.4M

Senior ASIC Engineer
3 profiles
Rs 2,603,595
Rs 0Rs 2.6M

Verification Specialist
3 profiles
Rs 850,000
Rs 0Rs 850K

Senior ASIC Design Engineer
3 profiles
Rs 2,700,000
Rs 0Rs 2.7M

See all employers for Verilog Vhdl »
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  • Country: India
  • Currency: INR
  • Updated: 18 Nov 2017
  • Individuals Reporting: 142
  • View Table

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