Average Salary for Skill: Verilog Vhdl

Verilog Vhdl Median Salary by Job


Design Verification Engineer
45 profiles
Rs 1,013,021
Rs 354KRs 2.5M

Design Engineer
38 profiles
Rs 650,000
Rs 199KRs 1.8M

ASIC Design Engineer
10 profiles
Rs 575,000
Rs 242KRs 1.8M

India (change)

Staff Engineer
4 profiles
Rs 2,437,500
Rs 0Rs 2.4M

Verification Specialist
3 profiles
Rs 850,000
Rs 0Rs 850K

Senior ASIC Design Engineer
3 profiles
Rs 2,700,000
Rs 0Rs 2.7M

Senior ASIC Engineer
2 profiles
Rs 2,549,020
Rs 0Rs 2.5M

See all employers for Verilog Vhdl »
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  • Country: India
  • Currency: INR
  • Updated: 14 Oct 2017
  • Individuals Reporting: 134
  • View Table

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