Average Salary for Skill: Verilog Vhdl

Skill: Verilog Vhdl Median Salary by Job
National Salary Data 
Rs 0Rs 900KRs 1MRs 2M
Design Verification EngineerRs 999,897  
Design EngineerRs 650,000  
ASIC Design EngineerRs 575,000  
Staff EngineerRs 2,437,500  
Verification SpecialistRs 850,000  
Senior ASIC Design EngineerRs 2,700,000  
Senior ASIC EngineerRs 2,549,020  
Country: India | Currency: INR | Updated: 23 Sep 2017 | Individuals Reporting: 134

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