Average Salary by Degree/Major Subject for Skill: Verilog Vhdl

Verilog Vhdl Median Salary by Degree/Major Subject

Rs 0Rs 3.6M

Rs 999,947

Rs 867,500

Rs 866,667

India (change)

Rs 2,000,000

Rs 511,226

Rs 500,000

Rs 950,000

Rs 816,000

Rs 460,000

Rs 1,450,000

Rs 3,650,000

Doctorate (PhD)
2 profiles
Rs 3,650,000

  Precise  
  Estimated  
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  • Country: India
  • Currency: INR
  • Updated: 20 Jan 2018
  • Individuals Reporting: 103
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