Average Salary by Degree/Major Subject for Skill: Verilog Vhdl

Verilog Vhdl Median Salary by Degree/Major Subject

Rs 0Rs 2.8M

bachelor of engineering (beng / be)
21 profiles
Rs 1,049,640

Master of Technology (MTech)
9 profiles
Rs 600,000

Bachelor of Technology (BT / BTech)
8 profiles
Rs 1,252,500

India (change)

Master of science (ms)
8 profiles
Rs 2,250,000

Bachelor of Science, Electrical Engineering (BSEE)
2 profiles
Rs 1,450,000

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  • Country: India
  • Currency: INR
  • Updated: 22 Oct 2017
  • Individuals Reporting: 45
  • View Table

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