Average Salary by Degree/Major Subject for Skill: Verilog Vhdl

Verilog Vhdl Median Salary by Degree/Major Subject

Rs 0Rs 2.8M

Bachelor of Engineering (BEng / BE)
22 profiles
Rs 1,024,390

Master of Technology (MTech)
10 profiles
Rs 1,050,000

Bachelor of Technology (BT / BTech)
9 profiles
Rs 1,155,000

India (change)

Master of Science (MS)
8 profiles
Rs 2,250,000

Bachelor of Science, Electrical Engineering (BSEE)
2 profiles
Rs 1,450,000

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  • Country: India
  • Currency: INR
  • Updated: 18 Nov 2017
  • Individuals Reporting: 47
  • View Table

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