Average Salary for Skill: verilog

verilog Median Salary by Job

MinMax

Design Verification Engineer
108 profiles
Rs 928,565
Rs 294KRs 2.4M

Design Engineer
25 profiles
Rs 480,000
Rs 175KRs 1.5M

ASIC Design Engineer
15 profiles
Rs 650,000
Rs 307KRs 1.2M

India (change)

Staff Engineer
14 profiles
Rs 2,095,238
Rs 1MRs 3.3M

Senior ASIC Design Engineer
8 profiles
Rs 1,422,888
Rs 822KRs 2.3M

Very-Large-Scale Integration (VLSI) Engineer
3 profiles
Rs 960,000
Rs 0Rs 960K

Principal Engineer, Semiconductor
3 profiles
Rs 3,500,000
Rs 0Rs 3.5M

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  • Country: India
  • Currency: INR
  • Updated: 11 Nov 2017
  • Individuals Reporting: 199
  • View Table

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