ASIC Design Engineer with Verilog Vhdl Skills Salary

The average pay for an ASIC Design Engineer with Verilog Vhdl skills is $98,114 per year. Most people with this job move on to other positions after 20 years in this field. Experience has a moderate effect on salary for this job.

$66,940 - $152,051
$67K
$100K
$150K
MEDIAN: $101,486
10%
50%
90%

Add this chart to your site: 640px    300px

$0$152K
Salary $66,940 - $152,051
Bonus $0.00 - $20,180
Profit Sharing $4,000
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
$69,065 - $152,605
  • Country: United States
  • Currency: USD
  • Updated: 12 Sep 2017
  • Individuals Reporting: 27

Find Out Exactly What You Should Be Paid

United States (change)

ASIC Design Engineer Job Listings

Key Stats for ASIC Design Engineer

Gender

Female
18 %
Male
82 %

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 2 votes.
Less than 1 year
7%
1-4 years
34%
5-9 years
31%
10-19 years
24%
20 years or more
3%
ADVERTISEMENT
Location:
Years in Fields/Career:
United States (change)

Experience Affects ASIC Design Engineer Salaries

Experienced
▲15%

National Average
$104,000

Mid-Career
▼2%

Entry-Level
▼18%

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 2 votes.

Gender

Female
18 %
Male
82 %

Years of Experience

Less than 1 year
7%
1-4 years
34%
5-9 years
31%
10-19 years
24%
20 years or more
3%

Common Health Benefits

medical benefits
Medical: 88%
dental benefits
Dental: 77%
vision benefits
Vision: 81%
no benefits
None: 8%
ADVERTISEMENT