ASIC Design Engineer with Verilog Vhdl Skills Salary
The average pay for an ASIC Design Engineer with Verilog Vhdl skills is $98,114 per year. Most people with this job move on to other positions after 20 years in this field. Experience has a moderate effect on salary for this job.
|Salary||$66,940 - $152,051|
|Bonus||$0.00 - $20,180|
|Total Pay (||$69,065 - $152,605|
ASIC Design Engineer Job Listings
Key Stats for ASIC Design Engineer
Rated 4 out of 5
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