Senior ASIC Design Engineer with Verilog Vhdl Skills Salary

The average salary for a Senior ASIC Design Engineer with Verilog Vhdl skills is $121,306 per year.

$79,660 - $153,610
$80K
$120K
$150K
MEDIAN: $122,291
10%
50%
90%

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$0$161K
Salary $79,660 - $153,610
Bonus $11,700
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
$79,660 - $161,305
  • Country: United States
  • Currency: USD
  • Updated: 15 Oct 2017
  • Individuals Reporting: 12

Senior ASIC Design Engineer Job Listings

Pay Difference by Location

National Average: $122,291

Larger city markers indicate a job is popular in that location.

Key Stats for Senior ASIC Design Engineer

Job Satisfaction

Extremely satisfied
Rated 5 out of 5
based on 2 votes.
5-9 years
17%
10-19 years
75%
20 years or more
8%

Experience Affects Senior ASIC Design Engineer Salaries

Experienced
▲4%

National Average
$122,000

Late-Career
▼4%

Entry-Level
▼16%

Job Satisfaction

Extremely satisfied
Rated 5 out of 5
based on 2 votes.

Years of Experience

5-9 years
17%
10-19 years
75%
20 years or more
8%

Common Health Benefits

medical benefits
Medical: 100%
dental benefits
Dental: 100%
vision benefits
Vision: 80%
no benefits
None: