The average pay for an Experienced Senior ASIC Design Engineer is Rs 2,082,500 per year. A skill in verilog is associated with high pay for this job.

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Pay Difference by Location

National Average: Rs 2,082,500

Larger city markers indicate a job is popular in that location.

Key Stats for Senior ASIC Design Engineer

10-19 years
Years in Fields/Career:
United States (change)

Skills That Affect Senior ASIC Design Engineer Salaries


Verilog Vhdl

National Average
Rs 2,082,000

Engineering Design, Semiconductor

Common Health Benefits

medical benefits
Medical: 100%
dental benefits
Dental: 40%
vision benefits
Vision: 40%
no benefits