Design Verification Engineer in Hyderabad, Andhra Pradesh Salary (India)

A Design Verification Engineer in Hyderabad, Andhra Pradesh earns an average salary of Rs 960,000 per year. People in this job generally don't have more than 10 years' experience. Skills that are associated with high pay for this job are Perl and verilog.

Rs 346,873 - Rs 2,132,542
Rs 350K
Rs 720K
Rs 2M
MEDIAN: Rs 719,526
10%
50%
90%
Rs 0Rs 3M
Salary Rs 346,873 - Rs 2,132,542
Bonus Rs 2,553 - Rs 255,321
Profit Sharing Rs 223,584
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 349,049 - Rs 3,026,179
  • Country: India
  • Currency: INR
  • Updated: 18 Jan 2018
  • Individuals Reporting: 25

Job Description for Design Verification Engineer

A design verification engineer works to debug and verify designs and potential products as needed by their company. They attempt to identify and solve as many problems as possible with a product before its public launch; this includes using products in other ways than intended use to identify safety concerns, design flaws, and problem areas. A design verification engineer must be able to work on a wide range of projects in a variety of areas.

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Design Verification Engineer Tasks

  • Develop verification environments and processes.
  • Explain and communicate verification needs and results.
  • Create scripts to automate and test processes.
  • Write verification plans, test them and improve methodologies and toolsets.

Design Verification Engineer Job Listings

Key Stats for Design Verification Engineer

Gender

Female
10 %
Male
90 %
Less than 1 year
8%
1-4 years
40%
5-9 years
36%
10-19 years
16%

Experience Affects Design Verification Engineer Salaries

Mid-Career
▲60%

National Average
Rs 730,000

▼11%

Skills That Affect Design Verification Engineer Salaries

Perl
▲186%

verilog
▲78%

Verilog Vhdl
▲8%

National Average
Rs 730,000

Gender

Female
10 %
Male
90 %

Years of Experience

Less than 1 year
8%
1-4 years
40%
5-9 years
36%
10-19 years
16%

Common Health Benefits

medical benefits
Medical: 81%
dental benefits
Dental:
vision benefits
Vision:
no benefits
None: 19%