Design Verification Engineer in Hyderabad, Andhra Pradesh Salary (India)

A Design Verification Engineer in Hyderabad, Andhra Pradesh earns an average salary of Rs 960,000 per year. People in this job generally don't have more than 10 years' experience. Skills that are associated with high pay for this job are Perl and verilog.

Rs 349,049 - Rs 2,128,716
Rs 350K
Rs 710K
Rs 2M
MEDIAN: Rs 712,155
10%
50%
90%
Rs 0Rs 3M
Salary Rs 349,049 - Rs 2,128,716
Bonus Rs 155,000
Profit Sharing Rs 226,006
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 352,337 - Rs 3,020,749
  • Country: India
  • Currency: INR
  • Updated: 10 Sep 2017
  • Individuals Reporting: 16

Find Out Exactly What You Should Be Paid

United States (change)

Design Verification Engineer Job Listings

Key Stats for Design Verification Engineer

Gender

Female
14 %
Male
86 %
Less than 1 year
6%
1-4 years
38%
5-9 years
31%
10-19 years
25%
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Location:
Years in Fields/Career:
United States (change)

Experience Affects Design Verification Engineer Salaries

Mid-Career
▲62%

National Average
Rs 720,000

▼10%

Skills That Affect Design Verification Engineer Salaries

Perl
▲190%

verilog
▲81%

Verilog Vhdl
▲9%

National Average
Rs 720,000

Gender

Female
14 %
Male
86 %

Years of Experience

Less than 1 year
6%
1-4 years
38%
5-9 years
31%
10-19 years
25%

Common Health Benefits

medical benefits
Medical: 78%
dental benefits
Dental:
vision benefits
Vision:
no benefits
None: 22%
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