The average salary for a Design Verification Engineer in Bangalore, Karnataka is Rs 928,643 per year. Experience strongly influences pay for this job. Most people move on to other jobs if they have more than 20 years' experience in this career.

Rs 297,132 - Rs 2,351,332
Rs 300K
Rs 970K
Rs 2M
MEDIAN: Rs 974,770
10%
50%
90%
Rs 0Rs 2M
Salary Rs 297,132 - Rs 2,351,332
Bonus Rs 5,960 - Rs 293,614
Profit Sharing Rs 7,946 - Rs 293,614
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 300,500 - Rs 2,434,498
  • Country: India
  • Currency: INR
  • Updated: 18 Jan 2018
  • Individuals Reporting: 267

Job Description for Design Verification Engineer

A design verification engineer works to debug and verify designs and potential products as needed by their company. They attempt to identify and solve as many problems as possible with a product before its public launch; this includes using products in other ways than intended use to identify safety concerns, design flaws, and problem areas. A design verification engineer must be able to work on a wide range of projects in a variety of areas.

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Design Verification Engineer Tasks

  • Develop verification environments and processes.
  • Explain and communicate verification needs and results.
  • Create scripts to automate and test processes.
  • Write verification plans, test them and improve methodologies and toolsets.

Design Verification Engineer Job Listings

Key Stats for Design Verification Engineer

Gender

Female
5 %
Male
95 %

Job Satisfaction

Extremely satisfied
Rated 5 out of 5
based on 10 votes.
Less than 1 year
6%
1-4 years
54%
5-9 years
28%
10-19 years
12%

Experience Affects Design Verification Engineer Salaries

Experienced
▲139%

▲43%

National Average
Rs 1,014,000

▼19%

Skills That Affect Design Verification Engineer Salaries

▲8%

C++ Programming Language
▲7%

National Average
Rs 1,014,000

▼8%

▼10%

System Verilog
▼18%

uvm
▼22%

SystemVerilog
▼36%

C++
▼42%

Job Satisfaction

Extremely satisfied
Rated 5 out of 5
based on 10 votes.

Gender

Female
5 %
Male
95 %

Years of Experience

Less than 1 year
6%
1-4 years
54%
5-9 years
28%
10-19 years
12%

Common Health Benefits

medical benefits
Medical: 75%
dental benefits
Dental: 8%
vision benefits
Vision: 7%
no benefits
None: 25%