Experienced Design Verification Engineer Salary

The average pay for an Experienced Design Verification Engineer is $127,619 per year. A skill in uvm is associated with high pay for this job.

$104,900 - $162,698
$100K
$130K
$160K
MEDIAN: $130,009
10%
50%
90%

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$0$175K
Salary $104,900 - $162,698
Bonus $4,909 - $25,760
Profit Sharing $0.00 - $13,685
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
$112,235 - $175,757
  • Country: United States
  • Currency: USD
  • Updated: 19 Oct 2017
  • Individuals Reporting: 70

Design Verification Engineer Job Listings

Key Stats for Design Verification Engineer

Gender

Female
17 %
Male
83 %

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 6 votes.
10-19 years
94%
20 years or more
6%

Skills That Affect Design Verification Engineer Salaries

uvm
▲22%

▼0%

National Average
$143,000

Engineering Design, Semiconductor
▼3%

Perl
▼4%

C++ Programming Language
▼5%

C programming Language
▼7%

Verilog Vhdl
▼9%

Board Design / Debug
▼14%

C++
▼16%

C
▼21%

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 6 votes.

Gender

Female
17 %
Male
83 %

Common Health Benefits

medical benefits
Medical: 96%
dental benefits
Dental: 88%
vision benefits
Vision: 88%
no benefits
None: 4%