Entry-Level Design Verification Engineer in San Jose Salary

An Entry-Level Design Verification Engineer in San Jose, California earns an average salary of $103,380 per year.

$84,430 - $125,579
$84K
$110K
$130K
MEDIAN: $107,465
10%
50%
90%

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$0$137K
Salary $84,430 - $125,579
Bonus $1,000 - $17,500
Profit Sharing $5,000
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
$87,756 - $137,315
  • Country: United States
  • Currency: USD
  • Updated: 10 Sep 2017
  • Individuals Reporting: 22

Find Out Exactly What You Should Be Paid

United States (change)

About San Jose, California

Santa Clara County, California
1,026,919
Male:
518,317 (50.5%)
Female:
508,602 (49.5%)
San Jose (/ˌsæn hoʊˈzeɪ/; Spanish for Saint Joseph), originally Pueblo de San José de Guadalupe and officially the City of San José, is the third-largest city by population in California, the tenth-largest by population in the United States, and the county seat of Santa Clara County. San Jose is the largest city within the Bay Area and the largest city in Northern California. Before the arrival of the Spanish, the area around San Jose was inhabited by the Ohlone people. San Jose was founded on November 29, 1777, as San José de Guadalupe, the first civilian town in the Spanish colony of Alta California. The city served as a farming community to support Spanish military installations at San Francisco and Monterey. When California gained statehood in 1850, San Jose became the capital. After more than 150 years as a small farming community, the San Jose area in the mid-20th century contained some of...
San Jose:
$91,451
California:
$64,500
$1,757
San Jose:
$717,100
California:
$449,100
4.1%

Design Verification Engineer Job Listings

Key Stats for Design Verification Engineer

Gender

Female
11 %
Male
89 %

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 5 votes.
Less than 1 year
9%
1-4 years
59%
5-9 years
32%
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Location:
Years in Fields/Career:
United States (change)

Skills That Affect Design Verification Engineer Salaries

National Average
$114,000

verilog
▼7%

C++ Programming Language
▼9%

Verilog Vhdl
▼13%

C
▼14%

Perl
▼15%

C++
▼16%

C programming Language
▼22%

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 5 votes.

Gender

Female
11 %
Male
89 %

Common Health Benefits

medical benefits
Medical: 88%
dental benefits
Dental: 82%
vision benefits
Vision: 76%
no benefits
None: 12%
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