The average pay for an Entry-Level Design Verification Engineer is Rs 612,067 per year. Skills that are associated with high pay for this job are C++ Programming Language and Perl.

Rs 238,353 - Rs 1,534,365
Rs 240K
Rs 620K
Rs 2M
MEDIAN: Rs 616,294
10%
50%
90%
Rs 0Rs 1M
Salary Rs 238,353 - Rs 1,534,365
Bonus Rs 1,250 - Rs 154,839
Profit Sharing Rs 0.00 - Rs 682,108
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 240,827 - Rs 1,683,095
  • Country: India
  • Currency: INR
  • Updated: 19 Oct 2017
  • Individuals Reporting: 136

Design Verification Engineer Job Listings

Pay Difference by Location

National Average: Rs 620,732

Larger city markers indicate a job is popular in that location.

Key Stats for Design Verification Engineer

Gender

Female
7 %
Male
93 %
Less than 1 year
10%
1-4 years
74%
5-9 years
16%

Skills That Affect Design Verification Engineer Salaries

C++ Programming Language
▲34%

▲27%

System Verilog
▲1%

National Average
Rs 621,000

Verilog Vhdl
▼3%

▼4%

uvm
▼10%

SystemVerilog
▼11%

C++
▼30%

Gender

Female
7 %
Male
93 %

Common Health Benefits

medical benefits
Medical: 62%
dental benefits
Dental: 8%
vision benefits
Vision: 5%
no benefits
None: 38%