The average salary for a Mid-Career Design Verification Engineer is Rs 1,341,178 per year. The skills that increase pay for this job the most are uvm and SystemVerilog.

Rs 715,864 - Rs 2,416,915
Rs 720K
Rs 1M
Rs 2M
MEDIAN: Rs 1,398,663
10%
50%
90%
Rs 0Rs 2M
Salary Rs 715,864 - Rs 2,416,915
Bonus Rs 0.00 - Rs 231,668
Profit Sharing Rs 9,696 - Rs 298,999
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 712,585 - Rs 2,501,926
  • Country: India
  • Currency: INR
  • Updated: 9 Jan 2018
  • Individuals Reporting: 113

Job Description for Design Verification Engineer

A design verification engineer works to debug and verify designs and potential products as needed by their company. They attempt to identify and solve as many problems as possible with a product before its public launch; this includes using products in other ways than intended use to identify safety concerns, design flaws, and problem areas. A design verification engineer must be able to work on a wide range of projects in a variety of areas.

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Design Verification Engineer Tasks

  • Develop verification environments and processes.
  • Explain and communicate verification needs and results.
  • Create scripts to automate and test processes.
  • Write verification plans, test them and improve methodologies and toolsets.

Design Verification Engineer Job Listings

Pay Difference by Location

National Average: Rs 1,449,328

Larger city markers indicate a job is popular in that location.

Key Stats for Design Verification Engineer

Gender

Female
10 %
Male
90 %

Job Satisfaction

Extremely satisfied
Rated 5 out of 5
based on 4 votes.
5-9 years
89%
10-19 years
11%

Skills That Affect Design Verification Engineer Salaries

uvm
▲8%

SystemVerilog
▲3%

National Average
Rs 1,449,000

Verilog Vhdl
▼10%

System Verilog
▼14%

verilog
▼15%

Perl
▼17%

Job Satisfaction

Extremely satisfied
Rated 5 out of 5
based on 4 votes.

Gender

Female
10 %
Male
90 %

Common Health Benefits

medical benefits
Medical: 80%
dental benefits
Dental: 9%
vision benefits
Vision: 7%
no benefits
None: 19%