The average salary for a Mid-Career Design Verification Engineer is Rs 1,341,178 per year. The skills that increase pay for this job the most are uvm and SystemVerilog.

Rs 702,337 - Rs 2,498,925
Rs 700K
Rs 1M
Rs 3M
MEDIAN: Rs 1,385,518
10%
50%
90%
Rs 0Rs 2M
Salary Rs 702,337 - Rs 2,498,925
Bonus Rs 0.00 - Rs 199,332
Profit Sharing Rs -21.77 - Rs 295,898
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
Rs 706,470 - Rs 2,543,796
  • Country: India
  • Currency: INR
  • Updated: 15 Oct 2017
  • Individuals Reporting: 67

Design Verification Engineer Job Listings

Pay Difference by Location

National Average: Rs 1,437,310

Larger city markers indicate a job is popular in that location.

Key Stats for Design Verification Engineer

Gender

Female
9 %
Male
91 %
5-9 years
84%
10-19 years
16%

Skills That Affect Design Verification Engineer Salaries

uvm
▲9%

SystemVerilog
▲4%

National Average
Rs 1,437,000

Verilog Vhdl
▼10%

System Verilog
▼13%

verilog
▼14%

Perl
▼17%

Gender

Female
9 %
Male
91 %

Common Health Benefits

medical benefits
Medical: 80%
dental benefits
Dental: 10%
vision benefits
Vision: 7%
no benefits
None: 17%