Mid-Career Design Verification Engineer Salary

Median pay for Mid-Career Design Verification Engineers lies in the neighborhood of $112K per year. Cash earnings for Mid-Career Design Verification Engineers — which occasionally include more than $19K from bonuses and more than $10K from profit sharing — stretch from around $93K to approximately $150K. Men account for the majority of Mid-Career Design Verification Engineers who responded to the questionnaire — 88 percent to be exact. Almost all enjoy medical while a fair number get dental coverage. Vision coverage is also available to a strong majority. Job satisfaction for Mid-Career Design Verification Engineers is high. The data for this synopsis comes from respondents who took the PayScale salary survey.

$91,115 - $136,574
$91K
$110K
$140K
MEDIAN: $112,230
10%
50%
90%

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$0$150K
Salary $91,115 - $136,574
Bonus $2,035 - $19,000
Profit Sharing $96.96 - $10,365
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
$92,817 - $150,278
  • Country: United States
  • Currency: USD
  • Updated: 11 Jul 2017
  • Individuals Reporting: 80

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United States (change)

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Design Verification Engineer Job Listings

Pay Difference by Location

National Average: $119,463

Larger city markers indicate a job is popular in that location.

Surpassing the national average by 8 percent, Mid-Career Design Verification Engineers in San Jose receive some of the highest pay in the country. Mid-Career Design Verification Engineers will also find cushy salaries in Santa Clara (+2 percent). The lowest-paying market is Austin, which sits 4 percent below the national average.

Key Stats for Design Verification Engineer

Gender

Female
13 %
Male
88 %

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 13 votes.
5-9 years
75%
10-19 years
25%
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Location:
Years in Fields/Career:
United States (change)

Skills That Affect Design Verification Engineer Salaries

uvm
▲12%

▲1%

C++ Programming Language
▲1%

Engineering Design, Semiconductor
▲1%

C programming Language
▲1%

National Average
$119,000

Perl
▼1%

Verilog Vhdl
▼5%

C++
▼22%

C
▼27%

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 13 votes.

Gender

Female
13 %
Male
88 %

Common Health Benefits

medical benefits
Medical: 92%
dental benefits
Dental: 80%
vision benefits
Vision: 77%
no benefits
None: 8%
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