Mid-Career Design Verification Engineer Salary

Mid-Career Design Verification Engineers take home an average $110K annually. In the world of Mid-Career Design Verification Engineers, overall income ranges from $85K near the bottom to $144K at the top; this can include more than $19K from bonuses and more than $10K from profit sharing in exceptional cases. Work is enjoyable for Mid-Career Design Verification Engineers, who typically claim high levels of job satisfaction. The vast majority (84 percent) of Mid-Career Design Verification Engineers who answered the questionnaire are male. Medical benefits are awarded to nearly all, and most earn dental coverage.

$82,779 - $133,146
$83K
$110K
$130K
MEDIAN: $109,504
10%
50%
90%

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National Salary Data (?
XAll compensation data shown are gross 10th to 90th percentile ranges. Take the PayScale Survey to find out how location influences pay for this job.
)
$0$50K$100K$150K
Salary
$82,779 - $133,146  
   
Bonus
$1,968 - $19,315  
Profit Sharing
$-0.50 - $10,033  
Total Pay (?
XTotal Pay combines base annual salary or hourly wage, bonuses, profit sharing, tips, commissions, overtime pay and other forms of cash earnings, as applicable for this job. It does not include equity (stock) compensation, cash value of retirement benefits, or the value of other non-cash benefits (e.g. healthcare).
)
$84,992 - $143,926  
Country: United States | Currency: USD | Updated: 25 Mar 2017 | Individuals Reporting: 78

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United States (change)

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Pay Difference by Location

National Average: $115,083

Larger city markers indicate a job is popular in that location.

For those looking to make money, Mid-Career Design Verification Engineers in San Jose enjoy an exceptional pay rate, 13 percent above the national average. Mid-Career Design Verification Engineers will also find cushy salaries in Santa Clara (+6 percent).

Key Stats for Design Verification Engineer

Gender

Female
16 %
Male
84 %

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 11 votes.
5-9 years
78%
10-19 years
22%
Location:
Years in Fields/Career:
United States (change)

Skills That Affect Design Verification Engineer Salaries

uvm
▲17%

C++ Programming Language
▲5%

Engineering Design, Semiconductor
▲5%

C programming Language
▲5%

▲4%

Perl
▲3%

National Average
$115,000

Verilog Vhdl
▼1%

C++
▼19%

C
▼25%

Job Satisfaction

Highly satisfied
Rated 4 out of 5
based on 11 votes.

Gender

Female
16 %
Male
84 %

Common Health Benefits

medical benefits
Medical: 95%
dental benefits
Dental: 80%
vision benefits
Vision: 77%
no benefits
None: 5%